Solid-state imaging device and electronic apparatus

ABSTRACT

A solid-state imaging device includes a pixel region in which shared pixels which share pixel transistors in a plurality of photoelectric conversion portions are two-dimensionally arranged. The shared pixel transistors are divisionally arranged in a column direction of the shared pixels, the pixel transistors shared between neighboring shared pixels are arranged so as to be horizontally reversed or/and vertically crossed, and connection wirings connected to a floating diffusion portion, a source of a reset transistor and a gate of an amplification transistor in the shared pixels are arranged along the column direction.

CROSS REFERENCES TO RELATED APPLICATIONS

The present invention is a Continuation of application Ser. No.14/242,407, filed Apr. 1, 2014, which is a Continuation of applicationSer. No. 12/929,181, filed on Jan. 6, 2011, now U.S. Pat. No. 8,723,999,issued on May 13, 2014, and contains subject matter related to JapanesePatent Application JP 2010-017019 filed in the Japanese Patent Office onJan. 28, 2010, the entire contents of which are incorporated herein byreference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a CMOS type solid-state imaging deviceand an electronic apparatus including the solid-state imaging device,which is applicable to, for example, a camera or the like.

2. Description of the Related Art

As a solid-state imaging device, a CMOS solid-state imaging device isknown. Since the CMOS solid-state imaging device has a low power supplyvoltage and low power consumption, the CMOS solid-state imaging deviceis used in digital still cameras, digital video cameras, various mobileterminals such as a mobile phone including a camera therein, printers,and the like.

In the CMOS solid-state imaging device, a pixel arranged in a pixelregion includes a plurality of pixel transistors in addition tophotodiodes PD which are photoelectric conversion portions, unlike a CCDsolid-state imaging device. In a general unit pixel, the pixeltransistor includes four transistors, namely, a transfer transistorincluding a floating diffusion portion FD which is a voltage conversionportion, a reset transistor, an amplification transistor and a selectiontransistor. Alternatively, the pixel transistor includes threetransistors, namely, a transfer transistor, a reset transistor and anamplification transistor omitting the selection transistor. Since thephotodiodes and the plurality of pixel transistors are necessary as theunit pixel, it is difficult to reduce the size of the pixels.

However, recently, a technology necessarily including a so-calledmulti-pixel shared structure of sharing the pixel transistors among aplurality of pixels so as to suppress the size of an area occupied byone pixel other than the photodiode PD is used. FIG. 29 shows an exampleof a solid-state imaging device in which shared pixels aretwo-dimensionally arranged by the multi-pixel shared structure describedin Japanese Unexamined Patent Application Publication No. 2006-54276.The solid-state imaging device 91 is a four-pixel shared example inwhich photodiodes PD are arranged in a zigzag. In the solid-stateimaging device 91, sets of two obliquely neighboring photodiodes PDsharing one floating diffusion portion FD are two-dimensionallyarranged. The shared pixels include four photodiodes PD1 to PD4 arrangedin a zigzag by two sets neighboring in a vertical direction and twocircuit groups (pixel transistors) in pixel transistor forming regions114 divided at upper and lower positions of one set.

Transfer gate electrodes TG [TG1 to TG4] are formed between the floatingdiffusion portions FD and two photodiodes PD sandwiching the floatingdiffusion portions FD therebetween of two sets. In the shared pixels,the two sets are electrically connected to the two circuit groups in thepixel transistor regions 94 through a connection wiring 92 so as toshare the four photodiodes PD1 to PD4 in the vertical direction. Thatis, the floating diffusion portions FD1 and FD2, a gate electrode (notshown) of the amplification transistor and a source (not shown) of thereset transistor are connected by the connection wiring 92 (so-called FDwiring) along the vertical direction.

The related art of the CMOS solid-state imaging device are disclosed inJapanese Unexamined Patent Application Publication Nos. 2004-172950,2005-157953, 2009-135319, 2003-31785, and 2005-223860.

In the Japanese Unexamined Patent Application Publication Nos.2004-172950 and 2005-157953, a CMOS solid-state imaging device in whichtwo pixels are shared is disclosed.

In the Japanese Unexamined Patent Application Publication No.2009-135319, a CMOS solid-state imaging device in which two pixelslocated in a vertical direction and two pixels located in a horizontaldirection, namely, a total of four pixels are shared.

In the Japanese Unexamined Patent Application Publication No.2003-31785, a back-illuminated type CMOS solid-state imaging device isdisclosed.

In the Japanese Unexamined Patent Application Publication No.2003-31785, a CMOS solid-state imaging device for performing verticalstripe correction is disclosed.

SUMMARY OF THE INVENTION

As the configuration of the shared pixel shown in FIG. 29, aconfiguration in which, among the pixel transistors divided as shown inFIG. 30, a reset transistor Tr2 is arranged on an upper side and aserial circuit of an amplification transistor Tr3 and a selectiontransistor Tr4 is arranged on a lower side is considered. The resettransistor Tr2 includes a reset gate electrode 106, a source region 104and a drain region 105. The amplification transistor Tr3 has anamplification gate electrode 109, and configures diffusion regions 116and 117 as a source region and a drain region. The selection transistorTr4 has a selection gate electrode 118, and configures diffusion regions115 and 116 as a source region and a drain region.

The reset transistor Tr2 and the serial circuit of the amplificationtransistor Tr3 and the selection transistor Tr4 are formed in the samelayout in each column of the shared pixel. Tr11 to Tr14 denote transfertransistors. In the shared pixel of each column, the two floatingdiffusion portions FD1 and FD2, the amplification gate electrode 109 andthe source region 104 of the reset transistor Tr2 are electricallyconnected by the FD lines 92A and 92B.

In the layout of the pixel transistors, in the amplification transistorTr3, the gate length is preferably as long as possible from theviewpoint of random noise. The amplification transistor Tr3 and theselection transistor Tr4 have to be arranged at a constant interval d1.

The diffusion regions which become the source/drain regions of theserial circuit of the amplification transistor Tr3 and the selectiontransistor Tr4 have to be arranged at a constant interval d2 so as to beelectrically isolated from the diffusion regions of the same serialcircuit of the shared pixel of the neighboring column.

Whenever the array of the shared pixels is increased, symmetry betweenthe shared photodiode PD and the serial circuit of the amplification andselection transistors is broken. As a result, the wiring length of theFD line 92A and 92B connecting the floating diffusion portions FD1 andFD2 is different in each column of the shared pixel as denoted by framesA and B of FIG. 30 and a difference in conversion efficiency betweencolumns occurs. In terms of image quality, since a difference insensitivity between columns appears, a vertical stripe occurs.

FIGS. 31 and 32 show an example of a longitudinal four-pixel shared typeCMOS solid-state imaging device as another pixel shared type. In thesolid-state imaging device 81 shown in FIG. 31, sets sharing twophotodiodes PD neighboring in a vertical (longitudinal) direction and afloating diffusion portion FD are two-dimensionally arranged. The sharedpixel is formed by arranging four longitudinally arranged photodiodesPD1 to PD4 of two sets neighboring in the vertical direction and pixeltransistors corresponding to two pixel columns of a lower side of eachset. Transfer transistors Tr11 to Tr14 are arranged in correspondencewith the photodiodes PD1 to PD4.

Each transfer gate electrode TG is commonly formed with a transfer gateelectrode of a neighboring column. In the pixel transistors arranged ona lower side of each set having two photodiodes PD, a serial circuit ofan amplification transistor Tr3 and a selection transistor Tr4 and areset transistor Tr2 are formed along a row direction. That is, in theshared pixel of neighboring columns, the serial circuit of theamplification transistor Tr3 and the selection transistor Tr4 and thereset transistor Tr2 are lined up and respectively arranged in the rowdirection. The FD lines 92A and 92B are arranged respectively in theshown layout. In FIG. 31, the portions corresponding to FIG. 30 aredenoted by the same reference numerals and the description thereof willbe omitted.

In the solid-state imaging device 82 shown in FIG. 32, the layout of thepixel transistors arranged on the lower side of each set having twophotodiodes PD is different from FIG. 31. That is, only a serial circuitof an amplification transistor Tr3 and a selection transistor Tr4 islined up and arranged on a lower side of one set in the same rowdirection and only a reset transistor Tr2 is lined up and arranged on alower side of the other set in the same row direction. That is, in theshared pixel of neighboring columns, the serial circuit of theamplification transistor Tr3 and the selection transistor Tr4 and thereset transistor Tr2 are respectively arranged in the row direction inthe same orientation. The FD lines 92A and 92B are respectively arrangedin the shown layout. In FIG. 32, the portions corresponding to FIG. 30are denoted by the same reference numerals and the description thereofwill be omitted.

As shown in FIGS. 31 and 32, in the solid-state imaging devices 81 and82, symmetry of the length of the FD lines 92A and 92B between columnsis broken, a difference in conversion efficiency between columns occurs,and a difference in sensitivity between rows occurs.

If, for example, color filters of a Bayer array are used, in any of thesolid-state imaging devices 100, 81 and 82 of FIGS. 30 to 32, since a Gbpixel and a pixel Gr which become green pixels are different in a region(area) overlapping with a gate electrode formed of polysilicon, adifference in light absorption of the gate electrode occurs and asensitivity difference occurs.

It is desirable to provide a solid-state imaging device in which asensitivity difference hardly occurs, in a solid-state imaging devicehaving shared pixels.

In addition, it is desirable to provide an electronic apparatusincluding the solid-state imaging device, which is applicable to acamera or the like.

A solid-state imaging device according to an embodiment of the presentinvention includes a pixel region in which shared pixels which sharepixel transistors in a plurality of photoelectric conversion portionsare two-dimensionally arranged. The shared pixel transistors aredivisionally arranged in a column direction of the shared pixels, andthe pixel transistors shared between neighboring shared pixels arearranged so as to be horizontally reversed or/and vertically crossed.Connection wirings (so-called FD wirings) connected to a floatingdiffusion portion, a source of a reset transistor and a gate of anamplification transistor in the shared pixels are arranged along thecolumn direction.

In the solid-state imaging device of the embodiment of the presentinvention, since the shared pixel transistors are divisionally arrangedin the column direction of the shared pixels and the pixel transistorsshared between the neighboring shared pixels are arranged so as to behorizontally reversed or/and vertically crossed, symmetry of everyshared pixel including the FD wirings is improved. For example, thewiring lengths of the FD wirings between the neighboring shared pixelsbecome equal, capacitance applied to the FD wirings becomes constant ineach shared pixel, and a difference in photoelectric conversionefficiency hardly occurs. In the case of using color filters of theBayer array, the area occupied by the gate electrodes included in the Grpixel and the Gb pixel become equal. Light absorption amounts of thegate electrodes become equal and a difference in sensitivity between theGr pixel and the Gb pixel hardly occurs.

An electronic apparatus according to another embodiment of the presentinvention includes a solid-state imaging device, an optical systemconfigured to guide incident light to a photoelectric conversion portionof the solid-state imaging device, and a signal processing circuitconfigured to process an output signal of the solid-state imagingdevice. The solid-state imaging device includes a pixel region in whichshared pixels which share pixel transistors in a plurality ofphotoelectric conversion portions are two-dimensionally arranged. Theshared pixel transistors are divisionally arranged in a column directionof the shared pixels, and the pixel transistors shared betweenneighboring shared pixels are arranged so as to be horizontally reversedor/and vertically crossed. Connection wirings connected to a floatingdiffusion portion, a source of a reset transistor and a gate of anamplification transistor in the shared pixels are arranged along thecolumn direction.

In the electronic apparatus of the present invention, since thesolid-state imaging devices of the above-described embodiments of thepresent invention are included, a difference in sensitivity between theshared pixels hardly occurs.

According to the solid-state imaging device of the embodiment of thepresent invention, in the solid-state imaging device having sharedpixels, it is possible to provide a solid-state imaging device havingshared pixels between which a difference in sensitivity hardly occurs.

According to the electronic apparatus of the embodiment of the presentinvention, since the solid-state imaging device having shared pixelsbetween which a difference in sensitivity hardly occurs is included, itis possible to obtain high quality and to provide an electronicapparatus with high reliability.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic configuration diagram of a CMOS solid-stateimaging device according to the present invention;

FIG. 2 is a configuration diagram of the main parts of a solid-stateimaging device according to a first embodiment of the present invention;

FIG. 3 is a configuration diagram of the main parts of a solid-stateimaging device according to Comparative Example 1;

FIGS. 4A & 4B is a configuration diagram of the main parts of asolid-state imaging device according to a second embodiment of thepresent invention;

FIG. 5 is a configuration diagram of the main parts of a solid-stateimaging device according to Comparative Example 2;

FIG. 6 is a configuration diagram of the main parts of a solid-stateimaging device according to a third embodiment of the present invention;

FIG. 7 is a configuration diagram of the main parts of a solid-stateimaging device according to Comparative Example 3;

FIGS. 8A & 8B is a configuration diagram of the main parts of asolid-state imaging device according to a fourth embodiment of thepresent invention;

FIG. 9 is a configuration diagram of the main parts of a solid-stateimaging device according to Comparative Example 4-1;

FIG. 10 is a configuration diagram of the main parts of a solid-stateimaging device according to Comparative Example 4-2;

FIGS. 11A & 11B is a configuration diagram of the main parts of asolid-state imaging device according to a fifth embodiment of thepresent invention;

FIG. 12 is a configuration diagram of the main parts of a solid-stateimaging device according to Comparative Example 5-1;

FIG. 13 is a configuration diagram of the main parts of a solid-stateimaging device according to Comparative Example 5-2;

FIG. 14 is a configuration diagram of the main parts of a solid-stateimaging device according to a sixth embodiment of the present invention;

FIG. 15 is a configuration diagram of the main parts of a solid-stateimaging device according to Comparative Example 6;

FIG. 16 is a configuration diagram of the main parts of a solid-stateimaging device according to a seventh embodiment of the presentinvention;

FIG. 17 is a configuration diagram of the main parts of a solid-stateimaging device according to Comparative Example 7;

FIG. 18 is a configuration diagram of the main parts of a solid-stateimaging device according to an eighth embodiment of the presentinvention;

FIG. 19 is a configuration diagram of the main parts of a solid-stateimaging device according to Comparative Example 8;

FIG. 20 is a configuration diagram of the main parts of a solid-stateimaging device according to a ninth embodiment of the present invention;

FIG. 21 is a configuration diagram of the main parts of a solid-stateimaging device according to Comparative Example 9;

FIG. 22 is an equivalent circuit diagram of a 4-pixel shared structureof a 3-transistor type;

FIG. 23 is an equivalent circuit diagram of a 4-pixel shared structureof a 4-transistor type;

FIG. 24 is an equivalent circuit diagram of a 2-pixel shared structureof a 3-transistor type;

FIG. 25 is an equivalent circuit diagram of a 2-pixel shared structureof a 4-transistor type;

FIG. 26 is an equivalent circuit diagram of a 2×2-pixel sharedstructure, that is, a 4-pixel shared structure, of a 3-transistor type;

FIG. 27 is an equivalent circuit diagram of a 2×2-pixel sharedstructure, that is, a 4-pixel shared structure, of a 4-transistor type;

FIG. 28 is a schematic configuration diagram of an electronic apparatusaccording to the present invention;

FIG. 29 is a configuration diagram of the main parts of a solid-stateimaging device of a zigzag 4-pixel shared structure of the related art;

FIG. 30 is a configuration diagram of the main parts of a solid-stateimaging device of a zigzag 4-pixel shared structure of the related art;

FIG. 31 is a configuration diagram of the main parts of a solid-stateimaging device of a 3-transistor type of longitudinal 4-pixel sharedstructure of the related art; and

FIG. 32 is a configuration diagram of the main parts of a solid-stateimaging device of a 4-transistor type of longitudinal 4-pixel sharedstructure of the related art.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, modes (hereinafter, referred to as embodiments) carryingout the present invention will be described. The description will begiven in the following order.

1. Schematic Configuration Example of CMOS Solid-state Imaging Device

2. Basic Configuration of Solid-state Imaging Device of Embodiment

3. First Embodiment (Configuration Example of Solid-state ImagingDevice)

4. Second Embodiment (Configuration Example of Solid-state ImagingDevice)

5. Third Embodiment (Configuration Example of Solid-state ImagingDevice)

6. Fourth Embodiment (Configuration Example of Solid-state ImagingDevice)

7. Fifth Embodiment (Configuration Example of Solid-state ImagingDevice)

8. Sixth Embodiment (Configuration Example of Solid-state ImagingDevice)

9. Seventh Embodiment (Configuration Example of Solid-state ImagingDevice)

10. Eighth Embodiment (Configuration Example of Solid-state ImagingDevice)

11. Ninth Embodiment (Configuration Example of Solid-state ImagingDevice)

12. Tenth Embodiment (Configuration Example of Electronic Apparatus)

1. Schematic Configuration Example of CMOS Solid-State Imaging Device

FIG. 1 shows the schematic configuration of an example of a CMOSsolid-state imaging device according to each embodiment of the presentinvention. The solid-state imaging device 1 of the present exampleincludes a pixel region (so-called imaging region) 3 in which aplurality of pixels 2 including photoelectric conversion portions isregularly and two-dimensionally arranged on a semiconductor substrate11, for example, a silicon substrate, and a peripheral circuit portion,as shown in FIG. 1. As the pixels 2, shared pixels in which a pluralityof photoelectric conversion portions share the other pixel transistorsexcept a transfer transistor are used. The plurality of pixeltransistors may include, for example, three transistors, namely atransfer transistor, a reset transistor and an amplification transistoror four transistors, namely, a transfer transistor, a reset transistor,an amplification transistor and a selection transistor.

The peripheral circuit portion includes a vertical driving circuit 4,column signal processing circuits 5, a horizontal driving circuit 6, anoutput circuit 7, a control circuit 8, and the like.

The control circuit 8 receives data for instructing an input clock, anoperation mode, and the like and outputs data such as internalinformation of the solid-state imaging device. That is, the controlcircuit 8 generates a clock signal or a control signal which is used asa reference signal of an operation of the vertical driving circuit 4,the column signal processing circuits 5, the horizontal driving circuit6, or the like according to a vertical synchronization signal, ahorizontal synchronization signal and a master clock. Such a signal isinput to the vertical driving circuit 4, the column signal processingcircuits 5, the horizontal driving circuit 6, or the like.

The vertical driving circuit 4 includes a shift register, selects apixel driving line, supplies a pulse signal for driving the pixels tothe selected pixel driving line, and drives the pixels in row units.That is, the vertical driving circuit 4 sequentially selects the pixels2 of the pixel region 3 in row units in a vertical direction. Pixelsignals based on signal charges generated according to a light receptionamount in, for example, photodiodes which are the photoelectricconversion elements of the pixels 2 are supplied to the column signalprocessing circuits 5 through vertical signal lines 9.

The column signal processing circuits 5 are arranged in, for example,every column of the pixel 2 so as to perform signal processing such asnoise elimination with respect to the signal output from the pixels 2corresponding to one row in each pixel column. That is, the columnsignal processing circuits 5 perform signal processing such as CDS,signal amplification, AD conversion, and the like, for eliminatinginherent fixed pattern noise of the pixel 2. Horizontal selectionswitches (not shown) are connected between output stages of the columnsignal processing circuits 5 and horizontal signal lines 10.

The horizontal driving circuit 6 includes, for example, a shiftregister, sequentially outputs a horizontal scanning pulse so as tosequentially select the column signal processing circuits 5, and outputsthe pixel signals from the column signal processing circuits 5 tohorizontal signal lines 10.

The output circuit 7 performs signal processing with respect to thesignals sequentially supplied from the column signal processing circuits5 through the horizontal signal lines 10 and outputs the processedsignals. For example, only buffering may be performed, black leveladjustment, column deviation correction, a variety of digital signalprocessing, and the like may be performed. An input/output terminal 12exchanges a signal with an external device.

In a front-illuminated type CMOS solid-state imaging device, a pluralityof shared pixels which shares the pixel transistors in photodiodes PD,which are a plurality of photoelectric conversion portions, is formed ina first conductive type semiconductor well region, for example, p-typesemiconductor well region corresponding to the pixel region of thesemiconductor substrate. Each shared pixel is partitioned in an elementisolation region. A multi-layer wiring layer having a plurality ofwiring layers with an interlayer insulating films interposedtherebetween is formed on a front surface side of the semiconductorsubstrate except on the photodiodes PD, and color filters and an on-chiplens are laminated and formed on the multi-layer wiring layer with aplanarization film interposed therebetween. Light is irradiated to thephotodiodes PD rather than the front surface side of the semiconductorsubstrate through the on-chip lens.

In a back-illuminated type CMOS solid-state imaging device, a pluralityof shared pixels which shares the pixel transistors in photodiodes PD,which are a plurality of photoelectric conversion portions, is formed ina thinned semiconductor substrate, that is, a semiconductor substrate inwhich a first conductive type semiconductor well region, that is, ap-type semiconductor well region is formed. Each shared pixel ispartitioned in an element isolation region. A multi-layer wiring layerhaving a plurality of wiring layers with an interlayer insulating filminterposed therebetween is formed on one surface side of thesemiconductor substrate, and a support substrate formed of asemiconductor substrate is adhered thereon. The wiring arrangement isnot limited and the wiring is formed even on photodiodes PD. Colorfilters and the on-chip lens are laminated and formed on a rear surfaceside of the semiconductor substrate. Light is irradiated to thephotodiodes PD rather than the rear surface side of the semiconductorsubstrate through the on-chip lens.

2. Basic Configuration of Solid-State Imaging Device of Embodiment

The solid-state imaging device according to the present embodiment, thatis, the CMOS solid-state imaging device includes shared pixels sharingpixel transistors in a plurality of photoelectric conversion portions.The shared pixels are regularly and two-dimensionally arranged so as toform a pixel region. The pixel transistors are configured as a3-transistor type including a transfer transistor, a reset transistorand an amplification transistor or a 4-transistor type further includinga selection transistor in addition to the 3-transistor type. Among thepixel transistors of the shared pixels, the transfer transistor includestransfer transistors equal in number to the number of photoelectricconversion portions and each of the other shared pixel transistors. Theshared pixel transistor, that is, the pixel transistors other than thetransfer transistors are divided and arranged in a column direction ofthe shared pixels.

In the present embodiment, between neighboring shared pixels, forexample, between shared pixels of neighboring columns or neighboringrows, the shared pixel transistors are horizontally reversed, arevertically crossed or are horizontally reversed and vertically crossed.A connection wiring, that is, an FD wiring, connected to a floatingdiffusion portion FD of each shared pixel, a source of a resettransistor and a gate of an amplification transistor is arranged along acolumn direction. A row direction denotes a direction along a row and acolumn direction denotes a direction along a column.

According to the solid-state imaging device according to the presentembodiment, between neighboring shared pixels in which the pixeltransistors shared within the shared pixels are divided and arranged inthe column direction, the shared pixel transistors are arranged so as tobe horizontally reversed and vertically crossed. By this configuration,symmetry of every shared pixel including the FD wiring of the sharedpixel is improved, a difference in wiring length of the FD wiringdisappears, and the wiring capacitance of the FD wiring becomes constantin every shared pixel. Accordingly, a difference in photoelectricconversion efficiency of every column or row hardly occurs and adifference in sensitivity between columns or rows disappears. As aresult, in terms of image quality, a vertical stripe that is not a lightamount of the photoelectric conversion portion until it is filled withcharge, but that is a so-called sensitivity light amount, disappears.

In the case of using a color filter of the Bayer array, betweenneighboring shared pixels, by arranging the shared pixel transistors tobe vertically crossed or to be horizontally reversed and to bevertically crossed, the occupied area of the base electrode overlappinga Gr pixel and a Gb pixel becomes equal. That is, the degree of lightabsorption by a gate electrode formed of a polysilicon becomes equal anda difference in sensitivity between the Gr pixel and the Gb pixel hardlyoccurs. Accordingly, it is possible to provide a solid-state imagingdevice with a plurality of shared pixels, in which a difference insensitivity hardly occurs.

3. First Embodiment Configuration Example of Solid-State Imaging Device

FIG. 2 shows a solid-state imaging device, that is, a CMOS solid-stateimaging device according to a first embodiment of the present invention.FIG. 2 shows the schematic configuration of main portions applied to theCMOS solid-state imaging device in which pixel transistors of the3-transistor type are provided and a plurality of shared pixels having azigzag 4-pixel shared structure is arranged. The present embodiment ischaracterized in the arrangement of the pixel transistors and will bedescribed in comparison with a Comparative Example 1 of FIG. 3.

FIG. 22 shows an equivalent circuit of the shared pixels having the4-pixel shared structure of the 3-transistor type. The shared pixelsaccording to the present example include four photodiodes PD [PD1 toPD4] which are the photoelectric conversion portions, four transfertransistors Tr1 [Tr1 to Tr14], one reset transistor Tr2, and oneamplification transistor Tr3. In the shared pixels, a first floatingdiffusion portion FD1 is shared between the two photodiodes PD1 and PD2and a second floating diffusion portion FD2 is shared between twophotodiodes PD3 and PD4.

The photodiodes PD1 to PD4 are connected to the transfer transistorsTr11 to Tr14, respectively. That is, two photodiodes PD1 and PD2 areconnected to the first floating diffusion portion FD1 through thetransfer transistors Tr11 and Tr12. Two photodiodes PD3 and PD4 areconnected to the second floating diffusion portion FD2 through thetransfer transistor Tr13 and Tr14. The first floating diffusion portionFD1 and the second floating diffusion portion FD2 are connected and theconnection point is connected to a source of the reset transistor Tr2and a gate of the amplification transistor Tr3. A drain of the resettransistor Tr2 is connected to a power source Vdd. A drain of theamplification transistor Tr3 is connected to the power source Vdd and asource thereof is connected to a vertical signal line 9.

First, a solid-state imaging device according to Comparative Example 1of FIG. 3 will be described. In the solid-state imaging device 101 ofComparative Example 1, sets sharing one floating diffusion portion FDbetween two obliquely neighboring photodiodes PD are two-dimensionallyarranged, and 4-pixel shared pixels 102 of the zigzag array areconfigured by two sets neighboring in a vertical (longitudinal)direction. That is, a first set sharing the first floating diffusionportion FD1 between two obliquely neighboring photodiodes PD1 and PD2and a second set sharing the second floating diffusion portion FD2between two obliquely neighboring photodiodes PD3 and PD4 are included.The first set and the second set are adjacently arranged in alongitudinal direction.

The transfer gate electrodes TG1 and TG2 are respectively formed betweenthe photodiodes PD1 and PD2 and the first floating diffusion portion FD1so as to form the first transfer transistor Tr11 and the second transfertransistor Tr12. The transfer gate electrodes TG3 and TG4 arerespectively formed between the photodiodes PD3 and PD4 and the secondfloating diffusion portion FD2 so as to form the third transfertransistor Tr13 and the fourth transfer transistor Tr14.

In the shared pixels 102, the reset transistor Tr2 and the amplificationtransistor Tr3 are arranged to be divided vertically. That is, the resettransistor Tr2 including a source region 104, a drain region 105 and areset gate electrode 106 is arranged on an upper side of a first sethaving the two photodiodes PD1 and PD2. In addition, an amplificationtransistor Tr3 including a source region 107, a drain region 108 and anamplification gate electrode 109 is arranged on an upper side of asecond set having the two photodiodes PD3 and PD4. The reset transistorTr2 and the amplification transistor Tr3 are arranged so as to bedeviated from each other in a row (lateral) direction of the sharedpixel 102.

Between the shared pixels neighboring in the row direction, that is,between the shared pixels 102 of the neighboring columns, the mutualamplification transistors Tr3 are lined up in the same direction and arearranged in the same row direction and the mutual reset transistors Tr2are lined up in the same direction and arranged in the same rowdirection. In the shared pixel 102 of one of the neighboring columns,the source region 104 of the reset transistor, the amplification gateelectrode 109 of the amplification transistor, the first floatingdiffusion portion FD1 and the second floating diffusion portion FD2 areconnected by an FD wiring 111A. In the shared pixel 102 of the other ofthe neighboring columns, the source region 104 of the reset transistor,the amplification gate electrode 109 of the amplification transistor,the first floating diffusion portion FD1 and the second floatingdiffusion portion FD2 are connected by an FD wiring 111B. In thesolid-state imaging device 101 of Comparative Example 1, the zigzag4-pixel shared pixels 102 of the 3-transistor type are configured by thefour photodiodes PD1 to PD4 of the zigzag array denoted by a broken line112 and the pixel transistors Tr11 to Tr14, Tr2 and Tr3.

In the solid-state imaging device 101 according to Comparative Example1, since the lengths of the FD wirings 111A and 111B of the sharedpixels 102 of the neighboring columns are identical, there is nodifference in conversion efficiency associated with the FD wiringlength. However, in the configuration having the color filter of theBayer array, as shown in FIG. 3, the Gb pixel includes the reset gateelectrode 106 formed of polysilicon of the reset transistor Tr2 in theshared pixels (that is, unit cells) 102. The Gr pixel includes theamplification gate electrode 109 formed of polysilicon of theamplification transistor Tr3 in the shared pixels (unit cells) 102. Thegate length of the amplification gate electrode 109 is greater than thatof the reset gate electrode 106. The Gr pixel and the Gb pixel are thesame green pixel, but include gate electrodes having different areas.Thus, a difference in light absorption between the Gr pixel and the Gbpixel occur due to the gate electrodes. As a result, a deviation insensitivity between columns occurs and thus a vertical stripe occurs.

Next, the solid-state imaging device according to the first embodimentwill be described. In the solid-state imaging device 21 of the firstembodiment, as shown in FIG. 2, sets sharing one floating diffusionportion FD between two obliquely neighboring photodiodes PD aretwo-dimensionally arranged, and 4-pixel shared pixels 22 of the zigzagarray are configured by two sets neighboring in a vertical direction.That is, a first set sharing the first floating diffusion portion FD1between two obliquely neighboring photodiodes PD1 and PD2 and a secondset sharing the second floating diffusion portion FD2 between twoobliquely neighboring photodiodes PD3 and PD4 are adjacently arranged ina longitudinal direction.

The transfer gate electrodes TG1 and TG2 are respectively formed betweenthe photodiodes PD1 and PD2 and the first floating diffusion portion FD1so as to form the first transfer transistor Tr11 and the second transfertransistor Tr12. The transfer gate electrodes TG3 and TG4 arerespectively formed between the photodiodes PD3 and PD4 and the secondfloating diffusion portion FD2 so as to form the third transfertransistor Tr13 and the fourth transfer transistor Tr14.

In the present embodiment, in the shared pixels 22, the reset transistorTr2 and the amplification transistor Tr3 are arranged to be dividedvertically. At this time, the mutual amplification transistors Tr3 arearranged between the shared pixels neighboring in the row direction,that is, the shared pixels 102 of the neighboring columns, so as to bevertically crossed and the mutual reset transistors Tr2 are arranged soas to be vertically crossed (see arrow). That is, the reset transistorTr2 and the amplification transistor Tr3 are lined up on the upper sideof the first set having the two photodiodes PD1 and PD2 of one columnand the upper side of the first set having the two photodiodes PD1 andPD2 of the other column. The amplification transistor Tr3 and the resettransistor Tr2 are lined up on the upper side of the second set havingthe two photodiodes PD3 and PD4 of one column and the other column suchthat the arrays of the reset transistor Tr2 and the amplificationtransistor Tr3 are vertically crossed. The reset transistor Tr2 and theamplification transistor Tr3 arranged vertically are arrangedsubstantially at the same positions without being deviated in the rowdirection.

The reset transistor Tr2 has a source region 24, a drain region 25 and areset gate electrode 26. The amplification transistor Tr3 has a sourceregion 27, a drain region 28 and an amplification gate electrode 29.

In the shared pixels 22 of one of the neighboring columns, the sourceregion 24 of the reset transistor, the amplification gate electrode 29of the amplification transistor, and the first and second floatingdiffusion portions FD1 and FD2 are electrically connected by an FDwiring 31A. In the shared pixels 22 of the other of the neighboringcolumns, the source region 24 of the reset transistor, the amplificationgate electrode 29 of the amplification transistor and the first andsecond floating diffusion portions FD1 and FD2 are electricallyconnected by an FD wiring 31B. In the present embodiment, the zigzag4-pixel shared pixels 22 of the 3-transistor type are configured by thefour photodiodes PD1 to PD4 of the zigzag array denoted by a broken line32 and the pixel transistors Tr11 to Tr14, Tr2 and Tr3.

According to the solid-state imaging device 21 according to the firstembodiment, the divisionally arranged reset transistor Tr2 andamplification transistors Tr3 are arranged so as to be verticallycrossed between the shared pixels 22 of the neighboring columns. By thisconfiguration, symmetry of every shared pixel including the FD wiring 31of the shared pixel 22 is improved, a difference in wiring length of theFD wiring 31A and 31B disappears, and the wiring capacitance of the FDwirings 31A and 31B becomes constant in every shared pixel. Accordingly,a difference in photoelectric conversion efficiency of each columnhardly occurs and a difference in sensitivity between columnsdisappears. As a result, a vertical stripe disappears.

In the case of using the color filter of the Bayer array, between theshared pixels of the neighboring columns, by arranging the resettransistor Tr2 and the amplification transistor Tr3 to be verticallycrossed, the respective reset gate electrodes 26 are included in the Grpixel and the Gb pixel. Since the reset gate electrodes 26 formed ofpolysilicon and having the same area are included in the Gr pixel andthe Gb pixel, a difference in light absorption does not occur due to thereset gate electrodes. As a result, the vertical stripe does not occur.Accordingly, it is possible to provide a solid-state imaging device witha plurality of shared pixels, in which a difference in sensitivitybetween the shared pixels hardly occurs.

4. Second Embodiment Configuration Example of Solid-State Imaging Device

FIG. 4 shows a solid-state imaging device, that is, a CMOS solid-stateimaging device according to a second embodiment of the presentinvention. FIG. 4 shows the schematic configuration of main portionsapplied to the CMOS solid-state imaging device in which pixeltransistors of the 4-transistor type are provided and a plurality ofshared pixels having a zigzag 4-pixel shared structure is arranged. Thearrangement of the pixel transistors and the like of the presentembodiment will be described in comparison with Comparative Example 2 ofFIG. 5.

FIG. 23 shows an equivalent circuit of the shared pixels having the4-pixel shared structure of the 4-transistor type. The shared pixelsaccording to the present example include four photodiodes PD [PD1 toPD4] which are the photoelectric conversion portions, four transfertransistors Tr1 [Tr11 to Tr14], one reset transistor Tr2, oneamplification transistor Tr3, and one selection transistor Tr4. A drainof the selection transistor Tr4 is connected to a source of theamplification transistor Tr3 and a source thereof is connected to avertical signal line 9. Since the other configuration has the sameconnection circuit as that described in FIG. 22, the portionscorresponding to FIG. 22 are denoted by the same reference numerals andthe description thereof will be omitted.

First, a solid-state imaging device according to Comparative Example 2of FIG. 5 will be described. The solid-state imaging device 114 ofComparative Example 2 is a CMOS solid-state imaging device having azigzag 4-pixel shared structure. The solid-state imaging device 114 ofComparative Example 2 is the same as Comparative Example 1 except thatthe pixel transistors of the 4-transistor type including the transfertransistor Tr1 [Tr11 to Tr14], the reset transistor Tr2, theamplification transistor Tr3 and the selection transistor Tr4 are used.In the solid-state imaging device 114 of the present comparativeexample, the reset transistor Tr2 is arranged on the upper side of thefirst set having the two photodiodes PD1 and PD2 and a serial circuit ofthe amplification transistor Tr3 and the selection transistor Tr4 isarranged on the upper side of the second set having the two photodiodesPD3 and PD4. This serial circuit includes diffusion regions 115, 116 and117 which become the source/drain regions, the amplification gateelectrode 109, and the selection gate electrode 118. That is, theamplification transistor Tr3 is formed by the diffusion regions 116 and117 as the source region and the drain region and the amplification gateelectrode 109. The selection transistor Tr4 is formed by the diffusionregions 115 and 116 as the source region and the drain region and theselection gate electrode 118. In the shared pixels 122 of theneighboring columns, the reset transistors Tr2 are lined up in the samedirection and are arranged in the same row direction and the serialcircuits of the amplification transistors Tr3 and the selectiontransistors Tr4 are lined up in the same direction and are arranged inthe same row direction.

Since the other configuration is the same as that described in FIG. 3,the portions corresponding to FIG. 3 are denoted by the same referencenumerals and the description thereof will be omitted.

In the solid-state imaging device 114 according to Comparative Example2, the wiring lengths of the FD wiring 111A of the shared pixel 122 ofthe left column and the FD wiring 111B of the shared pixel 122 of theright column are different in FIG. 5. That is, the FD wiring 111B of theright column is greater than the FD wiring 111A of the left column bythe length denoted by an elliptic frame C. Accordingly, a difference inwiring capacitance between the FD wiring 111A and the FD wiring 111Boccurs and thus conversion efficiency is different between the sharedpixels of the neighboring columns. As a result, a difference inconversion efficiency between columns occurs and thus a vertical stripeoccurs.

Next, the solid-state imaging device according to the second embodimentwill be described. The solid-state imaging device 34 of the secondembodiment is a CMOS solid-state imaging device having the zigzag4-pixel shared structure. The solid state imaging device 34 of thesecond embodiment includes the pixel transistors of the 4-transistortype including the transfer transistors Tr1 [TR11 to Tr14], the resettransistor Tr2, the amplification transistor Tr3 and the selectiontransistor Tr4.

In the solid-state imaging device 34 according to the second embodiment,as shown in FIG. 4, in each of the shared pixels of the neighboringcolumns, the reset transistor Tr2 is arranged on the upper side of thefirst set having the two photodiodes PD1 and PD2. In the shared pixelsof the neighboring columns, the serial circuits of the amplificationtransistor Tr3 and the selection transistor Tr4 are integrally arrangedon the upper side of the second set having the two photodiodes PD3 andPD4 so as to be horizontally reversed between the neighboring columns.That is, as shown in FIG. 4B, the drain regions of the amplificationtransistors Tr3 of the second serial circuits are formed of the commondiffusion region 37 and the serial circuits are arranged so as to behorizontally reversed between the shared pixels of the neighboringcolumns. The serial circuit includes the amplification transistor Tr3including the diffusion regions 36 and 37 as the source region and thedrain region and the amplification gate electrode 29 and the selectiontransistor Tr4 including the diffusion regions 35 and 36 as the sourceregion and the drain region and the selection gate electrode 38.

Since the other configuration has the same connection circuit as thatdescribed in the first embodiment, the portions corresponding to FIG. 2are denoted by the same reference numerals and the description thereofwill be omitted.

According to the solid-state imaging device 34 of the second embodiment,between the shared pixels 42 of the neighboring columns, the wiringlengths of the FD wiring 31A and the FD wiring 31B become equal.Accordingly, a difference in wiring capacitance between the FD wiring31A and the FD wiring 31B does not occur and a difference in conversionefficiency between columns does not occur. As a result, a difference insensitivity between columns does not occur and a vertical stripe doesnot occur. Accordingly, it is possible to provide a solid-state imagingdevice with a plurality of shared pixels, in which a difference insensitivity between the shared pixels hardly occurs.

5. Third Embodiment Configuration Example of Solid-State Imaging Device

FIG. 6 shows a solid-state imaging device, that is, a CMOS solid-stateimaging device according to a third embodiment of the present invention.FIG. 6 shows the schematic configuration of main portions applied to theCMOS solid-state imaging device in which pixel transistors of the4-transistor type are provided and a plurality of shared pixels having azigzag 4-pixel shared structure is arranged. The arrangement of thepixel transistors and the like of the present embodiment will bedescribed in comparison with a Comparative Example 3 of FIG. 7.

First, the solid-state imaging device according to Comparative Example 3of FIG. 7 will be described. The solid-state imaging device 124 ofComparative Example 3 is a CMOS solid-state imaging device having azigzag 4-pixel shared structure using color filters of the Bayer array.Since the other configuration is the same as that of the above-describedComparative Example 2 except that the Gr pixel and Gb pixel areincluded, the portions corresponding to FIG. 5 are denoted by the samereference numerals and the description thereof will be omitted.

In the solid-state imaging device 124 of Comparative Example 3, similarto that described in FIG. 5, the wiring lengths of the FD wiring 111A ofthe shared pixel 122 of the left column and the FD wiring 111B of theshared pixel 122 of the right column are different. That is, the FDwiring 111B of the right column is greater than the FD wiring 111A ofthe left column by the length denoted by an elliptic frame C.Accordingly, a difference in wiring capacitance between the FD wiring111A and the FD wiring 111B occurs and thus conversion efficiency isdifferent between the shared pixels of the neighboring columns. As aresult, a difference in conversion efficiency between columns occurs andthus a vertical stripe occurs.

In addition, the Gb pixel has a reset gate electrode 106 formed ofpolysilicon of the reset transistor Tr2 in the shared pixels 122. The Grpixel has an amplification gate electrode 109 formed of polysilicon ofthe amplification transistor Tr3 in the shared pixels 122. The gatelength of the amplification gate electrode 109 is greater than that ofthe reset gate electrode 106. The Gr pixel and the Gb pixel are the samegreen pixel, but include gate electrodes having different areas. Thus, adifference in light absorption between the Gr pixel and the Gb pixeloccurs due to the gate electrodes. As a result, a deviation insensitivity between columns occurs and thus a vertical stripe occurs.

Next, the solid-state imaging device according to the third embodimentwill be described. The solid-state imaging device 44 according to thethird embodiment is a CMOS solid-state imaging device having a zigzag4-pixel shared structure. The solid-state imaging device 44 of the thirdembodiment is the same as that of the second embodiment except that thearrangement of the pixel transistors is changed.

In the solid-state imaging device 44 according to the third embodiment,the serial circuits of the amplification transistor Tr3 and theselection transistor Tr4 are arranged between the shared pixels 45 ofthe neighboring columns so as to be vertically crossed without beinghorizontally reversed and, similarly, the reset transistors Tr2 arearranged so as to be vertically crossed (see arrow). That is, the resettransistor Tr2 and the serial circuit are lined up on the upper side ofthe first set having the two photodiodes PD1 and PD2 of one column andthe upper side of the first set having the two photodiodes PD1 and PD2of the other column. The serial circuit and the reset transistor Tr2 arelined up on the upper side of the second set having the two photodiodesPD3 and PD4 of one column and the other column such that the arrays ofthe reset transistor Tr2 and the serial circuit are vertically crossed.

Since the other configuration is the same as that of the secondembodiment, the portions corresponding to FIG. 4 are denoted by the samereference numerals and the description thereof will be omitted.

According to the solid-state imaging device 44 according to the thirdembodiment, the reset transistors Tr2 and the serial circuits of theamplification transistor Tr3 and the selection transistor Tr4 arearranged so as to be vertically crossed between the shared pixels 45 ofthe neighboring columns. By this configuration, the wiring lengths ofthe FD wiring 31A and the FD wiring 31B between the shared pixels 45 ofthe neighboring columns become equal, a difference in wiring capacitancebetween the FD wiring 31A and the FD wiring 31B does not occur, and adifference in conversion efficiency between columns does not occur. As aresult, a difference in sensitivity between columns disappears and avertical stripe does not occur.

In the case of using the color filters of the Bayer array, portions ofthe reset gate electrode 26 and the amplification gate electrode 29 arerespectively included in the Gr pixel and the Gb pixel according to theabove-described configuration. Since the portions of the reset gateelectrode 26 and the amplification gate electrode 29 formed ofpolysilicon and having the same area are included in the Gr pixel andthe Gb pixel, a difference in light absorption does not occur due to thereset gate electrodes. As a result, a vertical stripe does not occur.Accordingly, it is possible to provide a solid-state imaging devicehaving a 4-pixel shared structure, in which a difference in sensitivitybetween the shared pixels hardly occurs.

6. Fourth Embodiment Configuration Example of Solid-State Imaging Device

FIG. 8 shows a solid-state imaging device, that is, a CMOS solid-stateimaging device according to a fourth embodiment of the presentinvention. FIG. 8 shows the schematic configuration of main portionsapplied to the CMOS solid-state imaging device in which pixeltransistors of the 3-transistor type are provided and a plurality ofshared pixels having a longitudinal 4-pixel shared structure isarranged. The arrangement of the pixel transistors and the like of thepresent embodiment will be described in comparison with ComparativeExamples 4-1 and 4-2 of FIGS. 9 and 10.

First, Comparative Example 4-1 of FIG. 9 will be described. Thesolid-state imaging device 126 of Comparative Example 4-1 includesshared pixels having a longitudinal 4-pixel shared structure andincluding four photodiodes PD [PD1 to PD4] arranged in the vertical(longitudinal) direction. That is, a first set sharing a first floatingdiffusion portion FD1 between two longitudinally neighboring photodiodesPD1 and PD2 and a second set sharing a second floating diffusion portionFD2 between two longitudinally neighboring photodiodes PD3 and PD4 areincluded. The first set and the second set are adjacently arranged inthe vertical direction.

The transfer gate electrodes TG1 and TG2 are respectively formed betweenthe photodiodes PD1 and PD2 and the first floating diffusion portion FD1so as to form the first transfer transistor Tr11 and the second transfertransistor Tr12. The transfer gate electrodes TG3 and TG4 arerespectively formed between the photodiodes PD3 and PD4 and the secondfloating diffusion portion FD2 so as to form the third transfertransistor Tr13 and the fourth transfer transistor Tr14. The transfergate electrodes TG1 to TG4 are formed commonly with the transfer gateelectrodes TG1 to TG4 of the shared pixels of the neighboring column.

The amplification transistor Tr3 and the reset transistor Tr2 are linedup and arranged in the row direction on the lower side of the first setover the shared pixels 127 of the neighboring column and, similarly, theamplification transistor Tr3 and the reset transistor Tr2 are lined upand arranged in the row direction on the lower side of the second set.As shown, the FD wirings 111A and 111B are formed. Since the otherconfiguration is the same as that of the above-described comparativeexample, the portions corresponding thereto are denoted by the samereference numerals and the description thereof will be omitted.

In the solid-state imaging device 128 of Comparative Example 4-2 of FIG.10, the reset transistors Tr2 corresponding to the shared pixels of thecolumns are lined up and arranged in the row direction on the lower sideof the first set over the shared pixels 127 of the neighboring columns.In addition, the amplification transistors Tr3 corresponding to theshared pixels of the columns are lined up and arranged in the rowdirection on the lower side of the second set over the shared pixels 127of the neighboring columns. As shown, the FD wirings 111A and 111B areformed. Since the other configuration is the same as that of FIG. 9, theportions corresponding thereto are denoted by the same referencenumerals and the description thereof will be omitted.

In the solid-state imaging device 126 according to Comparative Example4-1 and the solid-state imaging device 128 of Comparative Example 4-2,the wiring lengths of the FD wiring 111A of the left shared pixel andthe FD wiring 111B of the right shared pixel are different. The wiringlengths are different due to the presence of the wiring portions denotedby elliptic frames E to G or an elliptic frame H. Accordingly, adifference in wiring capacitance occurs, a difference in conversionefficiency between columns occurs, and a vertical stripe occurs. In thecase of using the color filters of the Bayer array, since the areas ofthe gate electrodes included in the Gr pixel and the Gb pixel aredifferent, a difference in light absorption of the gate electrodes ofthe Gr pixel and the Gb pixel occurs. As a result, a deviation insensitivity between columns occurs and thus a vertical stripe occurs.

Next, the solid-state imaging device according to the fourth embodimentwill be described. The solid-state imaging device 47 of the fourthembodiment includes shared pixels having a longitudinal 4-pixel sharedstructure and including four photodiodes PD [PD1 to PD4] arranged in thevertical (longitudinal) direction, as shown in FIG. 8. That is, a firstset sharing a first floating diffusion portion FD1 between twolongitudinally neighboring photodiodes PD1 and PD2 and a second setsharing a second floating diffusion portion FD2 between twolongitudinally neighboring photodiodes PD3 and PD4 are included. Thefirst set and the second set are adjacently arranged in the verticaldirection.

The transfer gate electrodes TG1 and TG2 are respectively formed betweenthe photodiodes PD1 and PD2 and the first floating diffusion portion FD1so as to form the first transfer transistor Tr11 and the second transfertransistor Tr12. The transfer gate electrodes TG3 and TG4 arerespectively formed between the photodiodes PD3 and PD4 and the secondfloating diffusion portion FD2 so as to form the third transfertransistor Tr13 and the fourth transfer transistor Tr14. The transfergate electrodes TG1 to TG4 are formed commonly with the transfer gateelectrodes TG1 to TG4 of the shared pixels of the neighboring column.

In the present embodiment, the amplification transistors Tr3 of theshared pixels of the neighboring columns are horizontally reversed andthe respective drain regions 28 are commonly integrated. The resettransistors Tr2 of the shared pixels of the neighboring columns arehorizontally reversed and the respective drain regions 25 are commonlyintegrated. The horizontally reversed and integrated amplificationtransistors Tr3 and the horizontally reversed and integrated resettransistors Tr2 are arranged in the row direction. Simultaneously, thearray of the integrated amplification transistors Tr3 and the integratedreset transistors Tr2 is arranged so as to be vertically crossed betweenthe lower side of the first set and the lower side of the second set.

In the left shared pixel 48, the first floating diffusion portion FD1and the amplification gate electrode 29 of the upper stage and thesecond floating diffusion portion FD2 and the source region 24 of thereset transistor Tr2 of the lower stage are electrically connected by anFD wiring 31A. In the right shared pixel 48, the first floatingdiffusion portion FD1 and the source region 24 of the reset transistorTr2 of the upper stage and the second floating diffusion portion FD2 andthe amplification gate electrode 29 of the lower stage are electricallyconnected by an FD wiring 31B. Since the other configuration is the sameas that of the above-described embodiment, the portions correspondingthereto are denoted by the same reference numerals and the descriptionthereof will be omitted.

According to the solid-state imaging device 47 according to the fourthembodiment, by arranging the pixel transistors as described above, thewiring length of the FD wiring 31A of the shared pixel 48 of the leftcolumn and the FD wiring 31B of the shared pixel 48 of the right columnbecome equal. Accordingly, a difference in wiring capacitance betweenthe FD wirings 31A and 31B does not occur and a difference in conversionefficiency between columns does not occur. As a result, a verticalstripe does not occur.

In the case of using the color filters of the Bayer array, by arrangingthe pixel transistors as described above, the gate electrodes having thesame area are included in the Gr pixel and the Gb pixel. Accordingly, adifference in light absorption of the gate electrodes formed ofpolysilicon between the Gr pixel and the Gb pixel does not occur and avertical stripe does not occur. Accordingly, it is possible to provide asolid-state imaging device having a longitudinal 4-pixel sharedstructure, in which a difference in sensitivity between the sharedpixels hardly occurs.

7. Fifth Embodiment Configuration Example of Solid-State Imaging Device

FIG. 11 shows a solid-state imaging device, that is, a CMOS solid-stateimaging device according to a fifth embodiment of the present invention.FIG. 11 shows the schematic configuration of main portions applied tothe CMOS solid-state imaging device in which pixel transistors of the4-transistor type are provided and a plurality of shared pixels having alongitudinal 4-pixel shared structure is arranged. The arrangement ofthe pixel transistors and the like of the present embodiment will bedescribed in comparison with Comparative Examples 5-1 and 5-2 of FIGS.12 and 13.

First, the solid-state imaging device according to Comparative Example5-1 of FIG. 12 will be described. In the solid-state imaging device 131of Comparative Example 5-1, instead of the above-described array of thereset transistor and the amplification transistor of FIG. 9, the serialcircuit of the amplification transistor Tr3 and the selection transistorTr4 and the reset transistor Tr2 are arranged. The configuration of theserial circuit is the same as that described in FIG. 5. A referencenumeral 133 denotes the shared pixel. Since the other configuration isthe same as that of FIG. 9, the portions corresponding thereto aredenoted by the same reference numerals and the description thereof willbe omitted.

In the solid-state imaging device 132 of Comparative Example 5-2 of FIG.13, instead of the array of the reset transistors and the amplificationtransistors of FIG. 10, the reset transistors Tr2 and the serialcircuits of the amplification transistor Tr3 and the selectiontransistor Tr4 are arranged. The configuration of the serial circuit isthe same as that described in FIG. 5. A reference numeral 134 denotesthe shared pixel. Since the other configuration is the same as that ofFIG. 10, the portions corresponding thereto are denoted by the samereference numerals and the description thereof will be omitted.

In the solid-state imaging device 131 according to Comparative Example5-1 and the solid-state imaging device 132 of Comparative Example 5-2,the wiring lengths of the FD wiring 111A of the left shared pixel andthe FD wiring 111B of the right shared pixel are different. The wiringlengths are different due to the presence of the wiring portions denotedby elliptic frames E to G or an elliptic frame H. Accordingly, adifference in wiring capacitance occurs, a difference in conversionefficiency between columns occurs, and a vertical stripe occurs. In thecase of using the color filters of the Bayer array, since the areas ofthe gate electrodes included in the Gr pixel and the Gb pixel aredifferent, a difference in light absorption of the gate electrodes ofthe Gr pixel and the Gb pixel occurs. As a result, a deviation insensitivity between columns occurs and thus a vertical stripe occurs.

Next, the solid-state imaging device according to the fifth embodimentwill be described. In the solid-state imaging device 49 of the fifthembodiment, as shown in FIG. 11, the serial circuit of the amplificationtransistor Tr3 and the selection transistor Tr4 and the reset transistorTr2 are horizontally reversed in the shared pixels of the neighboringcolumns. The horizontally reversed serial circuit and reset transistorTr2 are arranged so as to be vertically crossed. That is, two resettransistors Tr2 in which the drain region 25 is commonly integrated andtwo serial circuits in which the drain region of the amplificationtransistor Tr3 is commonly integrated are arranged in the row directionon the lower side of the first set having two photodiodes PD1 and PD2.The integrated reset transistor Tr2 and the serial circuit are arrangedon the lower side of the second set having two photodiodes PD3 and PD4so as to become the array crossing the array of the integrated serialcircuit and reset transistor Tr2. The configuration of the serialcircuit is the same as that described in FIG. 4. A reference numeral 51denotes the shared pixel.

Since the other configuration is the same as that of FIG. 8, theportions corresponding to FIG. 8 are denoted by the same referencenumerals and the description thereof will be omitted.

According to the solid-state imaging device 49 according to the fifthembodiment, by arranging the pixel transistors as described above, thewiring length of the FD wiring 31A of the shared pixel 51 of the leftcolumn and the FD wiring 31B of the shared pixel 51 of the right columnbecome equal. Accordingly, a difference in wiring capacitance betweenthe FD wirings 31A and 31B does not occur and a difference in conversionefficiency between columns does not occur. As a result, a verticalstripe does not occur.

In the case of using the color filters of the Bayer array, by arrangingthe pixel transistors as described above, the gate electrodes having thesame area are included in the Gr pixel and the Gb pixel. Accordingly, adifference in light absorption of the gate electrodes formed ofpolysilicon between the Gr pixel and the Gb pixel does not occur and avertical stripe does not occur. Accordingly, it is possible to provide asolid-state imaging device having a longitudinal 4-pixel sharedstructure, in which a difference in sensitivity between the sharedpixels hardly occurs.

8. Sixth Embodiment Configuration Example of Solid-State Imaging Device

FIG. 14 shows a solid-state imaging device, that is, a CMOS solid-stateimaging device according to a sixth embodiment of the present invention.FIG. 14 shows the schematic configuration of the main parts applied tothe CMOS solid-state imaging device in which pixel transistors of the3-transistor type are provided and a plurality of shared pixels having alongitudinal 2-pixel shared structure is arranged. The arrangement ofthe pixel transistors and the like of the present embodiment will bedescribed in comparison with Comparative Example 6 of FIG. 15.

FIG. 24 shows an equivalent circuit of the shared pixels having pixeltransistors of the 3-transistor type and the 2-pixel shared structure.The portions corresponding to FIG. 22 are denoted by the same referencenumerals and the description thereof will be omitted.

First, Comparative Example 6 of FIG. 15 will be described. Thesolid-state imaging device according to Comparative Example 6 iscompleted by two-dimensionally arranging a plurality of shared pixels137 having a 2-pixel shared structure in which one floating diffusionportion FD is shared between vertically (longitudinally) neighboring twophotodiodes PD1 and PD2. Transfer gate electrodes are formed between thetwo photodiodes PD1 and PD2 and the floating diffusion portion FD so asto form transfer transistors Tr11 and Tr12. A reset transistor Tr2 andan amplification transistor Tr3 are arranged so as to be verticallydivided with the two photodiodes PD1 and PD2 interposed therebetween.The shared pixels 137 having the 2-pixel shared structure are formed ofthe two photodiodes PD1 and PD2, one floating diffusion portion FD, twotransfer transistors Tr11 and Tr12, one reset transistor Tr2 and oneamplification transistor Tr3.

The reset transistor Tr2 includes a source region 104, a drain region105 and a reset gate electrode 106. The amplification transistor Tr3includes a source region 107, a drain region 108 and an amplificationgate electrode 109. In the shared pixels 137 of the neighboring columns,the reset transistors Tr2 are lined up in the same direction andarranged in the same row direction and the amplification transistors Tr3are lined up in the same direction and arranged in the same rowdirection. In the shared pixels 137 of the columns, the FD wirings 111[111A and 111B] are electrically connected to the source regions 104 ofthe reset transistors Tr2, the floating diffusion portion FD and theamplification gate electrodes 109.

In the solid-state imaging device 136 of Comparative Example 6, thewiring lengths of the FD wirings 111A and 111B of the neighboringcolumns become equal. For example, in the case of using the colorfilters of the Bayer array, a portion of the reset gate electrode 106 isincluded in the Gr pixel and a portion of the amplification gateelectrode 109 is included in the Gb pixel. Since the Gr pixel and the Gbpixel include respective gate electrodes having different areas, adifference in light absorption of the gate electrodes between the Grpixel and the Gb pixel occurs. As a result, a deviation in sensitivitybetween columns occurs and a vertical stripe occurs.

Next, the solid-state imaging device according to the sixth embodimentof the present invention will be described. As shown in FIG. 14, thesolid-state imaging device 53 according to the sixth embodiment iscompleted by two-dimensionally arranging a plurality of shared pixels 54having a 2-pixel shared structure in which one floating diffusionportion FD is shared between two vertically (longitudinally) neighboringphotodiodes PD1 and PD2. Transfer gate electrodes TG1 and TG2 are formedbetween the two photodiodes PD1 and PD2 and the floating diffusionportion FD so as to form the transfer transistors Tr11 and Tr12.

In the present embodiment, the reset transistor Tr2 and theamplification transistor Tr3 are divisionally arranged on the upper andlower side of the shared pixels 54. In addition, the reset transistorTr2 and the amplification transistor Tr3 are lined up and arranged inthe row direction on the upper side of the shared pixels of theneighboring columns and the reset transistor Tr2 and the amplificationtransistor Tr3 are arranged on the lower side thereof such that thearray thereof crosses the array of the upper side. The reset transistorTr2 includes a source region 24, a drain region 25 and a reset gateelectrode 26. The amplification transistor Tr3 includes a source region27, a drain region 28 and an amplification gate electrode 29. In theshared pixels 54, the FD wirings 31 [31A and 31B] are electricallyconnected to the source regions 24 of the reset transistors Tr2, thefloating diffusion portion FD and the amplification gate electrodes 29.

According to the solid-state imaging device 53 according to the sixthembodiment, in the 2-pixel shared configuration, the reset transistorTr2 and the amplification transistor Tr3 are arranged so as to bevertically crossed between the shared pixels 54 of the neighboringcolumns. By this configuration, the wiring length of the FD wiring 31Aof the shared pixel 54 of the left column and the FD wiring 31B of theshared pixel 54 of the right column become equal. Accordingly, adifference in wiring capacitance between the FD wirings 31A and 31B doesnot occur and a difference in conversion efficiency between columns doesnot occur. As a result, a vertical stripe does not occur.

In the case of using the color filters of the Bayer array, by arrangingthe pixel transistors as described above, the gate electrodes having thesame area are included in the Gr pixel and the Gb pixel. Accordingly, adifference in light absorption of the gate electrodes formed ofpolysilicon between the Gr pixel and the Gb pixel does not occur and avertical stripe does not occur. Accordingly, it is possible to provide asolid-state imaging device having a 2-pixel shared structure, in which adifference in sensitivity between the shared pixels hardly occurs.

9. Seventh Embodiment Configuration Example of Solid-State ImagingDevice

FIG. 16 shows a solid-state imaging device, that is, a CMOS solid-stateimaging device according to a seventh embodiment of the presentinvention. FIG. 16 shows the schematic configuration of main portionsapplied to the CMOS solid-state imaging device in which pixeltransistors of the 4-transistor type are provided and a plurality ofshared pixels having a 2-pixel shared structure is arranged. Thearrangement of the pixel transistors and the like of the presentembodiment will be described in comparison with Comparative Example 7 ofFIG. 17.

FIG. 25 shows an equivalent circuit of the shared pixels having pixeltransistors of the 4-transistor type and the 2-pixel shared structure.The portions corresponding to FIG. 23 are denoted by the same referencenumerals and the description thereof will be omitted.

First, the solid-state imaging device according to Comparative Example 7of FIG. 17 will be described. In the solid-state imaging device 139 ofComparative Example 7, a reset transistor Tr2 and a serial circuit of anamplification transistor Tr3 and a selection transistor Tr4 aredivisionally arranged on the upper and lower sides of the shared pixels141. The reset transistor Tr2 includes a source region 104, a drainregion 105 and a reset gate electrode 106. The serial circuit of theamplification transistor Tr3 and the selection transistor Tr4 includethree diffusion regions 115, 116 and 117 which become the source/drainregions, an amplification gate electrode 109 and a selection gateelectrode 118. In the shared pixels 141 of the neighboring columns, thereset transistors Tr2 are arranged in the same direction and in the samerow direction and the serial circuit of the amplification transistor Tr3and the selection transistor Tr4 are arranged in the same direction andthe same row direction. Since the other configuration is the same asthat of FIG. 15, the portions corresponding to FIG. 15 are denoted bythe same reference numerals and the description thereof will be omitted.

In the solid-state imaging device 139 of Comparative Example 7, thewiring length of the FD wirings 111A and 111B of the neighboring columnsbecome equal. For example, in the case of using the color filters of theBayer array, a portion of the reset gate electrode 106 is included inthe Gr pixel and a portion of the amplification gate electrode 109 isincluded in the Gb pixel. Since the Gr pixel and the Gb pixel includethe gate electrodes having different areas, a difference in lightabsorption of the gate electrodes between the Gr pixel and the Gb pixeloccurs and, as a result, a deviation in sensitivity between columnsoccurs and a vertical stripe occurs.

Next, the solid-state imaging device according to the seventh embodimentwill be described. In the solid-state imaging device 56 according to theseventh embodiment, a reset transistor Tr2 and a serial circuit of anamplification transistor Tr3 and a selection transistor Tr4 aredivisionally arranged on the upper and lower sides of the shared pixels57. Between the shared pixels of the neighboring columns, the resettransistors Tr2 are arranged so as to be vertically crossed and theserial circuits are arranged so as to be vertical crossed. That is, thereset transistors Tr2 and the serial circuits of the amplificationtransistor Tr3 and the selection transistors Tr4 corresponding to theneighboring columns are lined up and arranged in the row direction suchthat the array thereof is arranged so as to be crossed on the upper sideand the lower side. The reset transistor Tr2 includes a source region24, a drain region 25 and a reset gate electrode 26. The serial circuitof the amplification transistor Tr3 and the selection transistor Tr4includes three diffusion regions 35, 36 and 37 which become thesource/drain regions, an amplification gate electrode 29 and a selectiongate electrode 38.

Since the other configuration is the same as that of FIG. 14, theportions corresponding to FIG. 14 are denoted by the same referencenumerals and the description thereof will be omitted.

According to the solid-state imaging device 56 according to the seventhembodiment, in the 2-pixel shared configuration, the reset transistorTr2 and the serial circuit of the amplification transistor Tr3 and theselection transistor Tr4 are arranged so as to be vertically crossedbetween the shared pixels 57 of the neighboring columns. By thisconfiguration, the wiring length of the FD wiring 31A of the sharedpixel 57 of the left column and the FD wiring 31B of the shared pixel 57of the right column become equal. Accordingly, a difference in wiringcapacitance between the FD wirings 31A and 31B does not occur and adifference in conversion efficiency between columns does not occur. As aresult, a vertical stripe does not occur.

In the case of using the color filters of the Bayer array, by arrangingthe pixel transistors as described above, the gate electrodes having thesame area are included in the Gr pixel and the Gb pixel. Accordingly, adifference in light absorption of the gate electrodes formed ofpolysilicon between the Gr pixel and the Gb pixel does not occur and avertical stripe does not occur. Accordingly, it is possible to provide asolid-state imaging device having a 2-pixel shared structure, in which adifference in sensitivity between the shared pixels hardly occurs.

10. Eighth Embodiment Configuration Example of Solid-State ImagingDevice

FIG. 18 shows a solid-state imaging device, that is, a CMOS solid-stateimaging device according to an eighth embodiment of the presentinvention. FIG. 18 shows the schematic configuration of main portionsapplied to the CMOS solid-state imaging device in which pixeltransistors of the 3-transistor type are provided and a plurality ofshared pixels having a 2×2 pixel shared structure, that is, a 4-pixelshared structure, is arranged. The arrangement of the pixel transistorsand the like of the present embodiment will be described in comparisonwith Comparative Example 8 of FIG. 19.

FIG. 26 shows an equivalent circuit of the shared pixels having pixeltransistors of the 3-transistor type and the 2×2-pixel shared structure,that is, the 4-pixel shared structure. The portions corresponding toFIG. 22 are denoted by the same reference numerals and the descriptionthereof will be omitted.

First, the solid-state imaging device according to Comparative Example 8of FIG. 19 will be described. In the solid-state imaging device 143 ofComparative Example 8, one floating diffusion portion FD is sharedbetween 2×2 photodiodes, that is, a total of four photodiodes PD [PD1 toPD4]. The pixel transistors are configured as the 3-transistor type offour transfer transistors Tr1 [Tr11 to Tr14], one reset transistor Tr2and one amplification transistor Tr3. The shared pixels 144 having the4-pixel shared structure are formed of the four photodiodes PD1 to PD4,one floating diffusion portion FD, the transfer transistors Tr11 toTr14, the reset transistor Tr2 and the amplification transistor Tr3.

Among the four transfer transistors Tr11 to Tr14, the transfer gateelectrodes of the transfer transistors Tr11 and Tr12 connected to twohorizontal photodiodes PD1 and PD2 are formed of a common gate electrodeTG1. The transfer gate electrodes of the transfer transistors Tr13 andTr14 connected to two horizontal photodiodes PD3 and PD4 are formed of acommon gate electrode TG2. The amplification transistor Tr3 and thereset transistor Tr2 are divisionally arranged on the upper side and thelower side of the shared pixels 144. In the vertically neighboringshared pixels 144, the reset transistors Tr2 are arranged in the samerow direction. The amplification transistors Tr3 are arranged in thesame row direction.

The reset transistor Tr2 includes a source region 104, a drain region105 and a reset gate electrode 106. The amplification transistor Tr3includes a source region 107, a drain region 108 and an amplificationgate electrode 109. In the shared pixels, the floating diffusion portionFD, the amplification gate electrode 109 and the source region 104 ofthe reset transistor are connected by the FD wirings 111 [111A and111B].

In the solid-state imaging device 143 of Comparative Example 8, the FDwirings 111A and 111B of the vertically neighboring shared pixels 144are formed along the column direction and the wiring lengths thereofbecome equal. For example, in the case of using the color filters of theBayer array, a portion of the reset gate electrode 106 is included inthe Gr pixel and a portion of the amplification gate electrode 109 isincluded in the Gb pixel. Since the Gr pixel and the Gb pixel includerespective gate electrodes having different areas, a difference in lightabsorption of the gate electrodes between the Gr pixel and the Gb pixeloccurs. As a result, a deviation in sensitivity between columns occursand a vertical stripe occurs.

Next, the solid-state imaging device according to the eighth embodimentwill be described. The solid-state imaging device 59 according to theeighth embodiment is configured by sharing one floating diffusionportion FD among the 2×2 photodiodes, that is, a total of fourphotodiodes PD [PD1 to PD4], as shown in FIG. 18. The pixel transistorsare configured as the 3-transistor type of the four transfer transistorsTr1 [Tr11 to Tr14], one reset transistor Tr2 and one amplificationtransistor Tr3. The shared pixels 61 having the 4-pixel shared structureare formed of the four photodiodes PD1 to PD4, one floating diffusionportion FD, the transfer transistors Tr11 to Tr14, the reset transistorTr2 and the amplification transistor Tr3.

Among the four transfer transistors Tr11 to Tr14, the transfer gateelectrodes of the transfer transistors Tr11 and Tr12 connected to twohorizontal photodiodes PD1 and PD2 are formed of a common gate electrodeTG1. The transfer gate electrodes of the transfer transistors Tr13 andTr14 connected to two horizontal photodiodes PD3 and PD4 are formed of acommon gate electrode TG2.

In the present embodiment, the two vertically neighboring shared pixelsare set as one and the reset transistor Tr2 and the amplificationtransistor Tr3 are divisionally arranged on the upper and lower sides inone set of shared pixels with the shared pixel 61 interposedtherebetween. In one set, the reset transistor Tr2 and the amplificationtransistor Tr3 lined up and arranged in the row direction so as tocorrespond to two shared pixels 61 are arranged such that the arraysthereof are crossed on the upper side and the lower side. The resettransistor Tr2 includes a source region 34, a drain region 35 and areset gate electrode 36. The amplification transistor Tr3 includes asource region 27, a drain region 28 and an amplification gate electrode29.

In the shared pixels 61, the FD wirings 31 [31A and 31B] areelectrically connected to the source region 24 of the reset transistorTr2, the floating diffusion portion FD and the amplification gateelectrode 29. The FD wirings 31A and 31B of the two verticallyneighboring shared pixels 61 are arranged along the column direction.

According to the solid-state imaging device 59 according to the eighthembodiment, the reset transistor Tr2 and the amplification transistorTr3 lined up and arranged in the row direction are arranged so as to bevertically crossed with the shared pixels 61 interposed therebetween.Accordingly, the wiring lengths of the FD wiring 31A and 31B of thevertically neighboring shared pixels 61 become equal. Accordingly, adifference in wiring capacitance between the FD wirings 31A and 31B doesnot occur and a difference in conversion efficiency between columns doesnot occur. As a result, a vertical stripe does not occur.

In the case of using the color filters of the Bayer array, by arrangingthe pixel transistors as described above, the gate electrodes having thesame area are included in the Gr pixel and the Gb pixel. Accordingly, adifference in light absorption of the gate electrodes formed ofpolysilicon between the Gr pixel and the Gb pixel does not occur and avertical stripe does not occur. Accordingly, it is possible to provide asolid-state imaging device having a 2-pixel shared structure, in which adifference in sensitivity between the shared pixels hardly occurs.

11. Ninth Embodiment Configuration Example of Solid-State Imaging Device

FIG. 20 shows a solid-state imaging device, that is, a CMOS solid-stateimaging device according to a ninth embodiment of the present invention.FIG. 20 shows the schematic configuration of main portions applied tothe CMOS solid-state imaging device in which pixel transistors of the4-transistor type are provided and a plurality of shared pixels having a2×2 pixel shared structure, that is, a 4-pixel shared structure, isarranged. The arrangement of the pixel transistors and the like of thepresent embodiment will be described in comparison with ComparativeExample 9 of FIG. 21.

FIG. 27 shows an equivalent circuit of the shared pixels having pixeltransistors of the 4-transistor type and the 2×2-pixel shared structure,that is, the 4-pixel shared structure. The portions corresponding toFIG. 23 are denoted by the same reference numerals and the descriptionthereof will be omitted.

First, the solid-state imaging device according to Comparative Example 9of FIG. 21 will be described. In the solid-state imaging device 146 ofComparative Example 9, a serial circuit of an amplification transistorTr3 and a selection transistor Tr4 and a reset transistor Tr2 aredivisionally arranged on the upper and lower sides with one shared pixelof the two vertically neighboring shared pixels 147 interposedtherebetween. Two reset transistors Tr2 corresponding to the two sharedpixels 64 are lined up and arranged in the same row direction. Twoserial circuits corresponding to the two shared pixels 64 are lined upand arranged in the same row direction. The configuration of the serialcircuit of the amplification transistor Tr3 and the selection transistorTr4 is the same as that of FIG. 13 described above.

Since the other configuration is the same as that of FIG. 19, theportions corresponding to FIG. 19 are denoted by the same referencenumerals and the description thereof will be omitted.

In the solid-state imaging device 146 of Comparative Example 9, the FDwirings 111A and 111B of the vertically neighboring shared pixels 147are formed along the column direction and the wiring lengths thereofbecome equal. For example, in the case of using the color filters of theBayer array, a portion of the reset gate electrode 106 is included inthe Gr pixel and a portion of the amplification gate electrode 109 andthe selection gate electrode 118 is included in the Gb pixel. Since theGr pixel and the Gb pixel include respective gate electrodes havingdifferent areas, a difference in light absorption of the gate electrodesbetween the Gr pixel and the Gb pixel occurs. As a result, a deviationin sensitivity between columns occurs and a vertical stripe occurs.

Next, the solid-state imaging device according to the ninth embodimentwill be described. In the solid-state imaging device 63 according to theninth embodiment, as shown in FIG. 20, the serial circuit of theamplification transistor Tr3 and the selection transistor Tr4 and thereset transistor Tr2 are horizontally reversed in the verticallyneighboring shared pixels. The horizontally reversed serial circuit andthe reset transistor Tr2 are arranged so as to be vertically crossed.That is, two reset transistors Tr2 in which the drain region 25 iscommonly integrated and two serial circuits in which the drain region ofthe amplification transistor Tr3 is commonly integrated are arranged inthe row direction on the upper side of the vertically neighboring sharedpixel 64. The integrated reset transistor Tr2 and the serial circuit arearranged on the lower side of the vertically neighboring shared pixel 64so as to become the array crossing the array of the integrated serialcircuit and reset transistor Tr2. The configuration of the integratedserial circuit and the integrated reset transistor Tr2 is the same asthat described in FIG. 5.

Since the other configuration is the same as that of FIG. 8, theportions corresponding to FIG. 8 are denoted by the same referencenumerals and the description thereof will be omitted.

According to the solid-state imaging device 63 according to the ninthembodiment, since the serial circuits and the reset transistors Tr2 ofthe vertically neighboring two shared pixels 64 are arranged so as to behorizontally reversed and vertically crossed, the wiring lengths of theFD wirings 31A and 31B of the vertically neighboring shared pixels 61become equal. Accordingly, a difference in wiring capacitance betweenthe FD wirings 31A and 31B does not occur and a difference in conversionefficiency between columns does not occur. As a result, a verticalstripe does not occur.

In the case of using the color filters of the Bayer array, by arrangingthe pixel transistors as described above, the gate electrodes having thesame area are included in the Gr pixel and the Gb pixel. Accordingly, adifference in light absorption of the gate electrodes formed ofpolysilicon between the Gr pixel and the Gb pixel does not occur and avertical stripe does not occur. Accordingly, it is possible to provide asolid-state imaging device having a 2-pixel shared structure, in which adifference in sensitivity between the shared pixels hardly occurs.

The solid-state imaging devices according to the above-describedembodiments of the present invention are applicable to afront-illuminated type or a back-illuminated type.

12. Tenth Embodiment Configuration Example of Electronic Apparatus

The above-described solid-state imaging devices according to the presentinvention are applicable to, for example, electronic apparatuses, suchas digital still cameras, digital video cameras, various mobileterminals such as mobile telephones including a camera included therein,printers or the like.

FIG. 28 shows a camera, which is an example of an electronic apparatus,according to a tenth embodiment of the present invention. The cameraaccording to the present embodiment is, for example, a video cameracapable of photographing a still image or a moving image. The camera 71of the present embodiment includes a solid-state imaging device 72, anoptical system 73 for guiding incident light to a light-receiving sensorunit of the solid-state imaging device 72, and a shutter device 74. Thecamera 71 further includes a driving circuit 75 for driving thesolid-state imaging device 72 and a signal processing circuit 76 forprocessing an output signal of the solid-state imaging device 72.

As the solid-state imaging device 72, any one of the solid-state imagingdevices of the above-described embodiments is applied. The opticalsystem (optical lens) 73 images image light (incident light) from asubject on a imaging surface of the solid-state imaging device 72 andthe optical system 73 may be an optical lens system including aplurality of optical lenses. The shutter device 74 controls a lightirradiation period and a light shielding period of the solid-stateimaging device 72. The driving circuit 75 supplies a driving signal forcontrolling a transmission operation of the solid-state imaging device72 and a shutter operation of the shutter device 74. Signal transmissionof the solid-state imaging device 72 is performed by the driving signal(timing signal) supplied from the driving circuit 75. The signalprocessing circuit 76 performs a variety of signal processes. Asignal-processed image signal is stored in a storage medium such as amemory or is output to a monitor.

According to the electronic apparatus such as the camera according tothe tenth embodiment, in the solid-state imaging device 72 having sharedpixels, since a difference in sensitivity between the shared pixelshardly occurs, it is possible to obtain high quality and to provide anelectronic apparatus with high reliability.

The present application contains subject matter related to thatdisclosed in Japanese Priority Patent Application JP 2010-017019 filedin the Japan Patent Office on Jan. 28, 2010, the entire contents ofwhich are hereby incorporated by reference.

It should be understood by those skilled in the art that variousmodifications, combinations, sub-combinations and alterations may occurdepending on design requirements and other factors insofar as they arewithin the scope of the appended claims or the equivalents thereof.

What is claimed is:
 1. An imaging device comprising: a first shared pixel including: a first plurality of photoelectric conversion portions, and a first transistor portion shared by the first plurality of photoelectric conversion portions, the first transistor portion including a first reset transistor, a first amplification transistor, and a first selection transistor; and a second shared pixel disposed adjacent to the first shared pixel and including: a second plurality of photoelectric conversion portions, and a second transistor portion shared by the second plurality of photoelectric conversion portions, the second transistor portion including a second reset transistor, a second amplification transistor, and a second selection transistor, wherein a gate terminal of the first selection transistor, a gate terminal of the first amplification transistor, a gate terminal of the second amplification transistor, and a gate terminal of the second selection transistor are adjacent one another in a first row in this order, and wherein a gate terminal of the first reset transistor and a gate terminal of the second reset transistor are disposed in a second row.
 2. The imaging device according to claim 1, wherein the first plurality of photoelectric conversion portions includes a first photoelectric conversion portion and a second photoelectric conversion portion, and the second plurality of photoelectric conversion portions includes a third photoelectric conversion portion and a fourth photoelectric conversion portion.
 3. The imaging device according to claim 2, wherein the first photoelectric conversion portion and the third photoelectric conversion portion are disposed in a third row, and the third row is disposed between the first row and the second row.
 4. The imaging device according to claim 2, wherein the first shared pixel includes a first floating diffusion shared by the first photoelectric conversion portion and the second photoelectric conversion portion, and the second shared pixel includes a second floating diffusion shared by the third photoelectric conversion portion and the fourth photoelectric conversion portion.
 5. The imaging device according to claim 4, wherein the first floating diffusion is connected to the first amplification transistor and the first reset transistor, and the second floating diffusion is connected to the second amplification transistor and the second reset transistor.
 6. The imaging device according to claim 4, wherein the first floating diffusion is connected to the first amplification transistor and the first reset transistor via a first floating diffusion line extending in a vertical direction, and the second floating diffusion is connected to the second amplification transistor and the second reset transistor via a second floating diffusion line extending in the vertical direction.
 7. The imaging device according to claim 1, wherein the first selection transistor is connected to a first vertical signal line at a first signal connection point, the second selection transistor is connected to a second vertical signal line at a second signal connection point, and the gate terminal of the first amplification transistor and the gate terminal of the second amplification transistor are disposed between the first signal connection point and the second signal connection point in the first row.
 8. The imaging device according to claim 1, wherein the first amplification transistor is connected to a power source line at a power connection point, and the power connection point is disposed between the gate terminal of the first amplification transistor and the gate terminal of the second amplification transistor in the first row.
 9. The imaging device according to claim 8, wherein the second amplification transistor is connected to the power source line at the power connection point.
 10. The imaging device according to claim 1, further comprising: a peripheral circuit portion including a vertical driving circuit, at least one column signal processing circuit, a horizontal driving circuit, an output circuit, and a control circuit.
 11. The imaging device according to claim 10, wherein the control circuit is configured to generate a clock signal or a control signal according to a vertical synchronization signal, a horizontal synchronization signal, and a master clock; and to provide the clock signal or the control signal to the vertical driving circuit, the at least one column signal processing circuit, and/or the horizontal driving circuit.
 12. The imaging device according to claim 10, wherein the vertical driving circuit is configured to drive the first shared pixel and the second shared pixel in row units.
 13. The imaging device according to claim 10, wherein the at least one column signal processing circuit includes a first column signal processing circuit connected to the first shared pixel, and a second column signal processing circuit connected to the second shared pixel.
 14. The imaging device according to claim 13, wherein the horizontal driving circuit is configured to sequentially select the first column signal processing circuit and the second column signal processing circuit, and to output a respective pixel signal from the corresponding column processing circuit to a corresponding horizontal signal line.
 15. The imaging device according to claim 10, wherein the output circuit is configured to perform signal processing on a respective signal supplied from the at least one column signal processing circuit, and to output the respective processed signal.
 16. The imaging device according to claim 1, further comprising: a semiconductor substrate including a first side as a light incident side and a second side opposite the first side, wherein the semiconductor substrate includes the first plurality of photoelectric conversion portions and the second plurality of photoelectric conversion portions; and a wiring layer disposed adjacent to the first side of the semiconductor substrate.
 17. The imaging device according to claim 1, further comprising: a semiconductor substrate including a first side as a light incident side and a second side opposite the first side, wherein the semiconductor substrate includes the first plurality of photoelectric conversion portions and the second plurality of photoelectric conversion portions; and a wiring layer disposed adjacent to the second side of the semiconductor substrate.
 18. An electronic apparatus comprising: an imaging device; an optical system configured to guide incident light to the imaging device; and a signal processing circuit configured to process an output signal of the imaging device, wherein the imaging device includes: a first shared pixel including: a first plurality of photoelectric conversion portions, and a first transistor portion shared by the first plurality of photoelectric conversion portions, the first transistor portion including a first reset transistor, a first amplification transistor, and a first selection transistor; and a second shared pixel disposed adjacent to the first shared pixel and including: a second plurality of photoelectric conversion portions, and a second transistor portion shared by the second plurality of photoelectric conversion portions, the second transistor portion including a second reset transistor, a second amplification transistor, and a second selection transistor, wherein a gate terminal of the first selection transistor, a gate terminal of the first amplification transistor, a gate terminal of the second amplification transistor, and a gate terminal of the second selection transistor are adjacent one another in a first row in this order, and wherein a gate terminal of the first reset transistor and a gate terminal of the second reset transistor are disposed in a second row.
 19. The electronic apparatus according to claim 18, wherein the first plurality of photoelectric conversion portions includes a first photoelectric conversion portion and a second photoelectric conversion portion, and the second plurality of photoelectric conversion portions includes a third photoelectric conversion portion and a fourth photoelectric conversion portion.
 20. The electronic apparatus according to claim 19, wherein the first photoelectric conversion portion and the third photoelectric conversion portion are disposed in a third row, and the third row is disposed between the first row and the second row.
 21. The electronic apparatus according to claim 19, wherein the first shared pixel includes a first floating diffusion shared by the first photoelectric conversion portion and the second photoelectric conversion portion, and the second shared pixel includes a second floating diffusion shared by the third photoelectric conversion portion and the fourth photoelectric conversion portion.
 22. The electronic apparatus according to claim 21, wherein the first floating diffusion is connected to the first amplification transistor and the first reset transistor, and the second floating diffusion is connected to the second amplification transistor and the second reset transistor.
 23. The electronic apparatus according to claim 21, wherein the first floating diffusion is connected to the first amplification transistor and the first reset transistor via a first floating diffusion line extending in a vertical direction, and the second floating diffusion is connected to the second amplification transistor and the second reset transistor via a second floating diffusion line extending in the vertical direction.
 24. The electronic apparatus according to claim 18, wherein the first selection transistor is connected to a first vertical signal line at a first signal connection point, the second selection transistor is connected to a second vertical signal line at a second signal connection point, and the gate terminal of the first amplification transistor and the gate terminal of the second amplification transistor are disposed between the first signal connection point and the second signal connection point in the first row.
 25. The electronic apparatus according to claim 18, wherein the first amplification transistor is connected to a power source line at a power connection point, and the power connection point is disposed between the gate terminal of the first amplification transistor and the gate terminal of the second amplification transistor in the first row.
 26. The electronic apparatus according to claim 25, wherein the second amplification transistor is connected to the power source line at the power connection point.
 27. The electronic apparatus according to claim 18, further comprising: a semiconductor substrate including a first side as a light incident side and a second side opposite the first side, wherein the semiconductor substrate includes the first plurality of photoelectric conversion portions and the second plurality of photoelectric conversion portions; and a wiring layer disposed adjacent to the first side of the semiconductor substrate. 